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Stabilize Ratified RISC-V Target Features
As shortly discussed on Zulip (https://rust-lang.zulipchat.com/#narrow/stream/250483-t-compiler.2Frisc-v/topic/Stabilization.20of.20RISC-V.20Target.20Features/near/394793704), this commit stabilizes the ratified RISC-V instruction bases and extensions. Specifically, this commit stabilizes the: * Instruction-Fetch Fence (Zifencei) on v2.0 * Control and Status Register (Zcsr) on v2.0 * Pause Hint (Zihintpause) on v2.0 * Zicntr and Zihpm were ratified March 2023 * Total Store Ordering (Ztso) on v1.0 * Supervisor-level Instructions (S) on v1.12 * Atomic Instructions (A) on v2.0 * Compressed Instructions (C) on v2.0 * Integer Multiplication and Division (M) on v2.0 * Bit Manipulations (B) on v1.0 listed as `zba`, `zbc`, `zbs` * Scalar Cryptography (Zk) v1.0.1 listed as `zk`, `zkn`, `zknd`, `zkne`, `zknh`, `zkr`, `zks`, `zksed`, `zksh`, `zkt`, `zbkb`, `zbkc` `zkbx`
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‎crates/std_detect/src/detect/arch/riscv.rs‎

Lines changed: 71 additions & 83 deletions
Original file line numberDiff line numberDiff line change
@@ -24,26 +24,48 @@ features! {
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///
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/// The supported ratified RISC-V instruction sets are as follows:
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///
27+
/// * RV32E: `"rv32e"`
2728
/// * RV32I: `"rv32i"`
28-
/// * Zifencei: `"zifencei"`
29-
/// * Zihintpause: `"zihintpause"`
3029
/// * RV64I: `"rv64i"`
31-
/// * M: `"m"`
3230
/// * A: `"a"`
33-
/// * Zicsr: `"zicsr"`
34-
/// * Zicntr: `"zicntr"`
35-
/// * Zihpm: `"zihpm"`
36-
/// * F: `"f"`
31+
/// * B: `"b"`
32+
/// * Zba: `"zba"`
33+
/// * Zbb: `"zbb"`
34+
/// * Zbc: `"zbc"`
35+
/// * Zbs: `"zbs"`
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/// * C: `"c"`
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/// * D: `"d"`
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/// * F: `"f"`
39+
/// * M: `"m"`
3840
/// * Q: `"q"`
39-
/// * C: `"c"`
41+
/// * V: `"v"`
42+
/// * Zicntr: `"zicntr"`
43+
/// * Zicsr: `"zicsr"`
44+
/// * Zifencei: `"zifencei"`
45+
/// * Zihintpause: `"zihintpause"`
46+
/// * Zihpm: `"zihpm"`
47+
/// * Zk: `"zk"`
48+
/// * Zbkb: `"zbkb"`
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/// * Zbkc: `"zbkc"`
50+
/// * Zbkx: `"zbkx"`
51+
/// * Zkn: `"zkn"`
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/// * Zknd: `"zknd"`
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/// * Zkne: `"zkne"`
54+
/// * Zknh: `"zknh"`
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/// * Zkr: `"zkr"`
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/// * Zks: `"zks"`
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/// * Zksed: `"zksed"`
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/// * Zksh: `"zksh"`
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/// * Zkt: `"zkt"`
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///
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/// There's also bases and extensions marked as standard instruction set,
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/// but they are in frozen or draft state. These instruction sets are also
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/// reserved by this macro and can be detected in the future platforms.
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///
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/// Frozen RISC-V instruction sets:
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///
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/// * Zfh: `"zfh"`
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/// * Zfhmin: `"zfhmin"`
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/// * Zfinx: `"zfinx"`
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/// * Zdinx: `"zdinx"`
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/// * Zhinx: `"zhinx"`
@@ -52,14 +74,9 @@ features! {
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///
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/// Draft RISC-V instruction sets:
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///
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/// * RV32E: `"rv32e"`
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/// * RV128I: `"rv128i"`
57-
/// * Zfh: `"zfh"`
58-
/// * Zfhmin: `"zfhmin"`
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/// * B: `"b"`
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/// * J: `"j"`
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/// * P: `"p"`
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/// * V: `"v"`
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/// * Zam: `"zam"`
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///
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/// Defined by Privileged Specification:
@@ -70,94 +87,65 @@ features! {
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/// * Svinval: `"svinval"`
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/// * Hypervisor: `"h"`
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///
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/// # RISC-V Bit-Manipulation ISA-extensions
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///
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/// This document defined the following extensions:
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///
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/// * Zba: `"zba"`
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/// * Zbb: `"zbb"`
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/// * Zbc: `"zbc"`
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/// * Zbs: `"zbs"`
81-
///
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/// # RISC-V Cryptography Extensions
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///
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/// These extensions are defined in Volume I, Scalar & Entropy Source
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/// Instructions:
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///
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/// * Zbkb: `"zbkb"`
88-
/// * Zbkc: `"zbkc"`
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/// * Zbkx: `"zbkx"`
90-
/// * Zknd: `"zknd"`
91-
/// * Zkne: `"zkne"`
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/// * Zknh: `"zknh"`
93-
/// * Zksed: `"zksed"`
94-
/// * Zksh: `"zksh"`
95-
/// * Zkr: `"zkr"`
96-
/// * Zkn: `"zkn"`
97-
/// * Zks: `"zks"`
98-
/// * Zk: `"zk"`
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/// * Zkt: `"zkt"`
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///
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/// [ISA manual]: https://github.com/riscv/riscv-isa-manual/
102-
#[unstable(feature = "stdsimd", issue = "27731")]
103-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] rv32i: "rv32i";
91+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] rv32i: "rv32i";
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/// RV32I Base Integer Instruction Set
105-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zifencei: "zifencei";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zifencei: "zifencei";
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/// "Zifencei" Instruction-Fetch Fence
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zihintpause: "zihintpause";
95+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zihintpause: "zihintpause";
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/// "Zihintpause" Pause Hint
109-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] rv64i: "rv64i";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] rv64i: "rv64i";
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/// RV64I Base Integer Instruction Set
111-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] m: "m";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] m: "m";
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/// "M" Standard Extension for Integer Multiplication and Division
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] a: "a";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] a: "a";
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/// "A" Standard Extension for Atomic Instructions
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zicsr: "zicsr";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zicsr: "zicsr";
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/// "Zicsr", Control and Status Register (CSR) Instructions
117-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zicntr: "zicntr";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zicntr: "zicntr";
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/// "Zicntr", Standard Extension for Base Counters and Timers
119-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zihpm: "zihpm";
107+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zihpm: "zihpm";
120108
/// "Zihpm", Standard Extension for Hardware Performance Counters
121-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] f: "f";
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@FEATURE: #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] f: "f";
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/// "F" Standard Extension for Single-Precision Floating-Point
123-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] d: "d";
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@FEATURE: #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] d: "d";
124112
/// "D" Standard Extension for Double-Precision Floating-Point
125-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] q: "q";
113+
@FEATURE: #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] q: "q";
126114
/// "Q" Standard Extension for Quad-Precision Floating-Point
127-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] c: "c";
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@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] c: "c";
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/// "C" Standard Extension for Compressed Instructions
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130-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zfinx: "zfinx";
118+
@FEATURE: #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] zfinx: "zfinx";
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/// "Zfinx" Standard Extension for Single-Precision Floating-Point in Integer Registers
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@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zdinx: "zdinx";
120+
@FEATURE: #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] zdinx: "zdinx";
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/// "Zdinx" Standard Extension for Double-Precision Floating-Point in Integer Registers
134-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zhinx: "zhinx";
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@FEATURE: #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] zhinx: "zhinx";
135123
/// "Zhinx" Standard Extension for Half-Precision Floating-Point in Integer Registers
136-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zhinxmin: "zhinxmin";
124+
@FEATURE: #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] zhinxmin: "zhinxmin";
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/// "Zhinxmin" Standard Extension for Minimal Half-Precision Floating-Point in Integer Registers
138-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] ztso: "ztso";
126+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] ztso: "ztso";
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/// "Ztso" Standard Extension for Total Store Ordering
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141-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] rv32e: "rv32e";
129+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] rv32e: "rv32e";
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/// RV32E Base Integer Instruction Set
143131
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] rv128i: "rv128i";
144132
/// RV128I Base Integer Instruction Set
145-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zfh: "zfh";
133+
@FEATURE: #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] zfh: "zfh";
146134
/// "Zfh" Standard Extension for 16-Bit Half-Precision Floating-Point
147-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zfhmin: "zfhmin";
135+
@FEATURE: #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] zfhmin: "zfhmin";
148136
/// "Zfhmin" Standard Extension for Minimal Half-Precision Floating-Point Support
149-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] b: "b";
137+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] b: "b";
150138
/// "B" Standard Extension for Bit Manipulation
151139
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] j: "j";
152140
/// "J" Standard Extension for Dynamically Translated Languages
153141
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] p: "p";
154142
/// "P" Standard Extension for Packed-SIMD Instructions
155-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] v: "v";
143+
@FEATURE: #[unstable(feature = "riscv_ext_intrinsics", issue = "114544")] v: "v";
156144
/// "V" Standard Extension for Vector Operations
157145
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zam: "zam";
158146
/// "Zam" Standard Extension for Misaligned Atomics
159147
160-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] s: "s";
148+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] s: "s";
161149
/// Supervisor-Level ISA
162150
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] svnapot: "svnapot";
163151
/// "Svnapot" Standard Extension for NAPOT Translation Contiguity
@@ -168,39 +156,39 @@ features! {
168156
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] h: "h";
169157
/// Hypervisor Extension
170158
171-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zba: "zba";
159+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zba: "zba";
172160
/// "Zba" Standard Extension for Address Generation Instructions
173-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbb: "zbb";
161+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zbb: "zbb";
174162
/// "Zbb" Standard Extension for Basic Bit-Manipulation
175-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbc: "zbc";
163+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zbc: "zbc";
176164
/// "Zbc" Standard Extension for Carry-less Multiplication
177-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbs: "zbs";
165+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zbs: "zbs";
178166
/// "Zbs" Standard Extension for Single-Bit instructions
179167
180-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbkb: "zbkb";
168+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zbkb: "zbkb";
181169
/// "Zbkb" Standard Extension for Bitmanip instructions for Cryptography
182-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbkc: "zbkc";
170+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zbkc: "zbkc";
183171
/// "Zbkc" Standard Extension for Carry-less multiply instructions
184-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbkx: "zbkx";
172+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zbkx: "zbkx";
185173
/// "Zbkx" Standard Extension for Crossbar permutation instructions
186-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zknd: "zknd";
174+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zknd: "zknd";
187175
/// "Zknd" Standard Extension for NIST Suite: AES Decryption
188-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zkne: "zkne";
176+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zkne: "zkne";
189177
/// "Zkne" Standard Extension for NIST Suite: AES Encryption
190-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zknh: "zknh";
178+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zknh: "zknh";
191179
/// "Zknh" Standard Extension for NIST Suite: Hash Function Instructions
192-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zksed: "zksed";
180+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zksed: "zksed";
193181
/// "Zksed" Standard Extension for ShangMi Suite: SM4 Block Cipher Instructions
194-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zksh: "zksh";
182+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zksh: "zksh";
195183
/// "Zksh" Standard Extension for ShangMi Suite: SM3 Hash Function Instructions
196-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zkr: "zkr";
184+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zkr: "zkr";
197185
/// "Zkr" Standard Extension for Entropy Source Extension
198-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zkn: "zkn";
186+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zkn: "zkn";
199187
/// "Zkn" Standard Extension for NIST Algorithm Suite
200-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zks: "zks";
188+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zks: "zks";
201189
/// "Zks" Standard Extension for ShangMi Algorithm Suite
202-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zk: "zk";
190+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zk: "zk";
203191
/// "Zk" Standard Extension for Standard scalar cryptography extension
204-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zkt: "zkt";
192+
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.74.0")] zkt: "zkt";
205193
/// "Zkt" Standard Extension for Data Independent Execution Latency
206194
}

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