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Thorsten Schütt
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[GlobalIsel] Modernize truncate of ext. (#100338)
Credits: #90964 https://reviews.llvm.org/D87050 combine-trunc.mir Functional changes intended.
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‎llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h‎

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -390,12 +390,6 @@ class CombinerHelper {
390390
void applyCombineExtOfExt(MachineInstr &MI,
391391
std::tuple<Register, unsigned> &MatchInfo);
392392

393-
/// Transform trunc ([asz]ext x) to x or ([asz]ext x) or (trunc x).
394-
bool matchCombineTruncOfExt(MachineInstr &MI,
395-
std::pair<Register, unsigned> &MatchInfo);
396-
void applyCombineTruncOfExt(MachineInstr &MI,
397-
std::pair<Register, unsigned> &MatchInfo);
398-
399393
/// Transform trunc (shl x, K) to shl (trunc x), K
400394
/// if K < VT.getScalarSizeInBits().
401395
///
@@ -886,6 +880,10 @@ class CombinerHelper {
886880

887881
bool matchShlOfVScale(const MachineOperand &MO, BuildFnTy &MatchInfo);
888882

883+
/// Transform trunc ([asz]ext x) to x or ([asz]ext x) or (trunc x).
884+
bool matchTruncateOfExt(const MachineInstr &Root, const MachineInstr &ExtMI,
885+
BuildFnTy &MatchInfo);
886+
889887
private:
890888
/// Checks for legality of an indexed variant of \p LdSt.
891889
bool isIndexedLoadStoreLegal(GLoadStore &LdSt) const;

‎llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -919,6 +919,21 @@ class GSUCmp : public GenericMachineInstr {
919919
};
920920
};
921921

922+
/// Represents an integer-like extending operation.
923+
class GExtOp : public GCastOp {
924+
public:
925+
static bool classof(const MachineInstr *MI) {
926+
switch (MI->getOpcode()) {
927+
case TargetOpcode::G_SEXT:
928+
case TargetOpcode::G_ZEXT:
929+
case TargetOpcode::G_ANYEXT:
930+
return true;
931+
default:
932+
return false;
933+
}
934+
};
935+
};
936+
922937
} // namespace llvm
923938

924939
#endif // LLVM_CODEGEN_GLOBALISEL_GENERICMACHINEINSTRS_H

‎llvm/include/llvm/Target/GlobalISel/Combine.td‎

Lines changed: 21 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -839,15 +839,6 @@ def unmerge_zext_to_zext : GICombineRule<
839839
(apply [{ Helper.applyCombineUnmergeZExtToZExt(*${d}); }])
840840
>;
841841

842-
// Fold trunc ([asz]ext x) -> x or ([asz]ext x) or (trunc x).
843-
def trunc_ext_fold_matchinfo : GIDefMatchData<"std::pair<Register, unsigned>">;
844-
def trunc_ext_fold: GICombineRule <
845-
(defs root:$root, trunc_ext_fold_matchinfo:$matchinfo),
846-
(match (wip_match_opcode G_TRUNC):$root,
847-
[{ return Helper.matchCombineTruncOfExt(*${root}, ${matchinfo}); }]),
848-
(apply [{ Helper.applyCombineTruncOfExt(*${root}, ${matchinfo}); }])
849-
>;
850-
851842
// Under certain conditions, transform:
852843
// trunc (shl x, K) -> shl (trunc x), K//
853844
// trunc ([al]shr x, K) -> (trunc ([al]shr (trunc x), K))
@@ -1768,6 +1759,25 @@ def freeze_combines: GICombineGroup<[
17681759
push_freeze_to_prevent_poison_from_propagating
17691760
]>;
17701761

1762+
/// Transform trunc ([asz]ext x) to x or ([asz]ext x) or (trunc x).
1763+
class truncate_of_opcode<Instruction extOpcode> : GICombineRule <
1764+
(defs root:$root, build_fn_matchinfo:$matchinfo),
1765+
(match (extOpcode $ext, $src):$ExtMI,
1766+
(G_TRUNC $root, $ext):$root,
1767+
[{ return Helper.matchTruncateOfExt(*${root}, *${ExtMI}, ${matchinfo}); }]),
1768+
(apply [{ Helper.applyBuildFn(*${root}, ${matchinfo}); }])>;
1769+
1770+
def truncate_of_zext : truncate_of_opcode<G_ZEXT>;
1771+
def truncate_of_sext : truncate_of_opcode<G_SEXT>;
1772+
def truncate_of_anyext : truncate_of_opcode<G_ANYEXT>;
1773+
1774+
def cast_combines: GICombineGroup<[
1775+
truncate_of_zext,
1776+
truncate_of_sext,
1777+
truncate_of_anyext
1778+
]>;
1779+
1780+
17711781
// FIXME: These should use the custom predicate feature once it lands.
17721782
def undef_combines : GICombineGroup<[undef_to_fp_zero, undef_to_int_zero,
17731783
undef_to_negative_one,
@@ -1828,7 +1838,7 @@ def constant_fold_binops : GICombineGroup<[constant_fold_binop,
18281838
def prefer_sign_combines : GICombineGroup<[nneg_zext]>;
18291839

18301840
def all_combines : GICombineGroup<[integer_reassoc_combines, trivial_combines,
1831-
vector_ops_combines, freeze_combines,
1841+
vector_ops_combines, freeze_combines, cast_combines,
18321842
insert_vec_elt_combines, extract_vec_elt_combines, combines_for_extload,
18331843
combine_extracted_vector_load,
18341844
undef_combines, identity_combines, phi_combines,
@@ -1839,7 +1849,7 @@ def all_combines : GICombineGroup<[integer_reassoc_combines, trivial_combines,
18391849
known_bits_simplifications, ext_ext_fold,
18401850
not_cmp_fold, opt_brcond_by_inverting_cond,
18411851
unmerge_merge, unmerge_cst, unmerge_dead_to_trunc,
1842-
unmerge_zext_to_zext, merge_unmerge, trunc_ext_fold, trunc_shift,
1852+
unmerge_zext_to_zext, merge_unmerge, trunc_shift,
18431853
const_combines, xor_of_and_with_same_reg, ptr_add_with_zero,
18441854
shift_immed_chain, shift_of_shifted_logic_chain, load_or_combine,
18451855
div_rem_to_divrem, funnel_shift_combines, bitreverse_shift, commute_shift,

‎llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp‎

Lines changed: 0 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -2582,40 +2582,6 @@ void CombinerHelper::applyCombineExtOfExt(
25822582
}
25832583
}
25842584

2585-
bool CombinerHelper::matchCombineTruncOfExt(
2586-
MachineInstr &MI, std::pair<Register, unsigned> &MatchInfo) {
2587-
assert(MI.getOpcode() == TargetOpcode::G_TRUNC && "Expected a G_TRUNC");
2588-
Register SrcReg = MI.getOperand(1).getReg();
2589-
MachineInstr *SrcMI = MRI.getVRegDef(SrcReg);
2590-
unsigned SrcOpc = SrcMI->getOpcode();
2591-
if (SrcOpc == TargetOpcode::G_ANYEXT || SrcOpc == TargetOpcode::G_SEXT ||
2592-
SrcOpc == TargetOpcode::G_ZEXT) {
2593-
MatchInfo = std::make_pair(SrcMI->getOperand(1).getReg(), SrcOpc);
2594-
return true;
2595-
}
2596-
return false;
2597-
}
2598-
2599-
void CombinerHelper::applyCombineTruncOfExt(
2600-
MachineInstr &MI, std::pair<Register, unsigned> &MatchInfo) {
2601-
assert(MI.getOpcode() == TargetOpcode::G_TRUNC && "Expected a G_TRUNC");
2602-
Register SrcReg = MatchInfo.first;
2603-
unsigned SrcExtOp = MatchInfo.second;
2604-
Register DstReg = MI.getOperand(0).getReg();
2605-
LLT SrcTy = MRI.getType(SrcReg);
2606-
LLT DstTy = MRI.getType(DstReg);
2607-
if (SrcTy == DstTy) {
2608-
MI.eraseFromParent();
2609-
replaceRegWith(MRI, DstReg, SrcReg);
2610-
return;
2611-
}
2612-
if (SrcTy.getSizeInBits() < DstTy.getSizeInBits())
2613-
Builder.buildInstr(SrcExtOp, {DstReg}, {SrcReg});
2614-
else
2615-
Builder.buildTrunc(DstReg, SrcReg);
2616-
MI.eraseFromParent();
2617-
}
2618-
26192585
static LLT getMidVTForTruncRightShiftCombine(LLT ShiftTy, LLT TruncTy) {
26202586
const unsigned ShiftSize = ShiftTy.getScalarSizeInBits();
26212587
const unsigned TruncSize = TruncTy.getScalarSizeInBits();

‎llvm/lib/CodeGen/GlobalISel/CombinerHelperCasts.cpp‎

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -113,3 +113,51 @@ bool CombinerHelper::matchNonNegZext(const MachineOperand &MO,
113113

114114
return false;
115115
}
116+
117+
bool CombinerHelper::matchTruncateOfExt(const MachineInstr &Root,
118+
const MachineInstr &ExtMI,
119+
BuildFnTy &MatchInfo) {
120+
const GTrunc *Trunc = cast<GTrunc>(&Root);
121+
const GExtOp *Ext = cast<GExtOp>(&ExtMI);
122+
123+
if (!MRI.hasOneNonDBGUse(Ext->getReg(0)))
124+
return false;
125+
126+
Register Dst = Trunc->getReg(0);
127+
Register Src = Ext->getSrcReg();
128+
LLT DstTy = MRI.getType(Dst);
129+
LLT SrcTy = MRI.getType(Src);
130+
131+
if (SrcTy == DstTy) {
132+
// The source and the destination are equally sized. We need to copy.
133+
MatchInfo = [=](MachineIRBuilder &B) { B.buildCopy(Dst, Src); };
134+
135+
return true;
136+
}
137+
138+
if (SrcTy.getScalarSizeInBits() < DstTy.getScalarSizeInBits()) {
139+
// If the source is smaller than the destination, we need to extend.
140+
141+
if (!isLegalOrBeforeLegalizer({Ext->getOpcode(), {DstTy, SrcTy}}))
142+
return false;
143+
144+
MatchInfo = [=](MachineIRBuilder &B) {
145+
B.buildInstr(Ext->getOpcode(), {Dst}, {Src});
146+
};
147+
148+
return true;
149+
}
150+
151+
if (SrcTy.getScalarSizeInBits() > DstTy.getScalarSizeInBits()) {
152+
// If the source is larger than the destination, then we need to truncate.
153+
154+
if (!isLegalOrBeforeLegalizer({TargetOpcode::G_TRUNC, {DstTy, SrcTy}}))
155+
return false;
156+
157+
MatchInfo = [=](MachineIRBuilder &B) { B.buildTrunc(Dst, Src); };
158+
159+
return true;
160+
}
161+
162+
return false;
163+
}

‎llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll‎

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -2659,9 +2659,9 @@ define i8 @atomicrmw_umin_i8(ptr %ptr, i8 %rhs) {
26592659
; CHECK-NOLSE-O1-NEXT: LBB35_1: ; %atomicrmw.start
26602660
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
26612661
; CHECK-NOLSE-O1-NEXT: ldaxrb w8, [x0]
2662-
; CHECK-NOLSE-O1-NEXT: and w10, w8, #0xff
2663-
; CHECK-NOLSE-O1-NEXT: cmp w10, w9
2664-
; CHECK-NOLSE-O1-NEXT: csel w10, w10, w9, lo
2662+
; CHECK-NOLSE-O1-NEXT: and w8, w8, #0xff
2663+
; CHECK-NOLSE-O1-NEXT: cmp w8, w9
2664+
; CHECK-NOLSE-O1-NEXT: csel w10, w8, w9, lo
26652665
; CHECK-NOLSE-O1-NEXT: stlxrb w11, w10, [x0]
26662666
; CHECK-NOLSE-O1-NEXT: cbnz w11, LBB35_1
26672667
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2674,9 +2674,9 @@ define i8 @atomicrmw_umin_i8(ptr %ptr, i8 %rhs) {
26742674
; CHECK-OUTLINE-O1-NEXT: LBB35_1: ; %atomicrmw.start
26752675
; CHECK-OUTLINE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
26762676
; CHECK-OUTLINE-O1-NEXT: ldaxrb w8, [x0]
2677-
; CHECK-OUTLINE-O1-NEXT: and w10, w8, #0xff
2678-
; CHECK-OUTLINE-O1-NEXT: cmp w10, w9
2679-
; CHECK-OUTLINE-O1-NEXT: csel w10, w10, w9, lo
2677+
; CHECK-OUTLINE-O1-NEXT: and w8, w8, #0xff
2678+
; CHECK-OUTLINE-O1-NEXT: cmp w8, w9
2679+
; CHECK-OUTLINE-O1-NEXT: csel w10, w8, w9, lo
26802680
; CHECK-OUTLINE-O1-NEXT: stlxrb w11, w10, [x0]
26812681
; CHECK-OUTLINE-O1-NEXT: cbnz w11, LBB35_1
26822682
; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2781,9 +2781,9 @@ define i8 @atomicrmw_umax_i8(ptr %ptr, i8 %rhs) {
27812781
; CHECK-NOLSE-O1-NEXT: LBB36_1: ; %atomicrmw.start
27822782
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
27832783
; CHECK-NOLSE-O1-NEXT: ldxrb w8, [x0]
2784-
; CHECK-NOLSE-O1-NEXT: and w10, w8, #0xff
2785-
; CHECK-NOLSE-O1-NEXT: cmp w10, w9
2786-
; CHECK-NOLSE-O1-NEXT: csel w10, w10, w9, hi
2784+
; CHECK-NOLSE-O1-NEXT: and w8, w8, #0xff
2785+
; CHECK-NOLSE-O1-NEXT: cmp w8, w9
2786+
; CHECK-NOLSE-O1-NEXT: csel w10, w8, w9, hi
27872787
; CHECK-NOLSE-O1-NEXT: stxrb w11, w10, [x0]
27882788
; CHECK-NOLSE-O1-NEXT: cbnz w11, LBB36_1
27892789
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -2796,9 +2796,9 @@ define i8 @atomicrmw_umax_i8(ptr %ptr, i8 %rhs) {
27962796
; CHECK-OUTLINE-O1-NEXT: LBB36_1: ; %atomicrmw.start
27972797
; CHECK-OUTLINE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
27982798
; CHECK-OUTLINE-O1-NEXT: ldxrb w8, [x0]
2799-
; CHECK-OUTLINE-O1-NEXT: and w10, w8, #0xff
2800-
; CHECK-OUTLINE-O1-NEXT: cmp w10, w9
2801-
; CHECK-OUTLINE-O1-NEXT: csel w10, w10, w9, hi
2799+
; CHECK-OUTLINE-O1-NEXT: and w8, w8, #0xff
2800+
; CHECK-OUTLINE-O1-NEXT: cmp w8, w9
2801+
; CHECK-OUTLINE-O1-NEXT: csel w10, w8, w9, hi
28022802
; CHECK-OUTLINE-O1-NEXT: stxrb w11, w10, [x0]
28032803
; CHECK-OUTLINE-O1-NEXT: cbnz w11, LBB36_1
28042804
; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3714,9 +3714,9 @@ define i16 @atomicrmw_umin_i16(ptr %ptr, i16 %rhs) {
37143714
; CHECK-NOLSE-O1-NEXT: LBB45_1: ; %atomicrmw.start
37153715
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
37163716
; CHECK-NOLSE-O1-NEXT: ldaxrh w8, [x0]
3717-
; CHECK-NOLSE-O1-NEXT: and w10, w8, #0xffff
3718-
; CHECK-NOLSE-O1-NEXT: cmp w10, w9
3719-
; CHECK-NOLSE-O1-NEXT: csel w10, w10, w9, lo
3717+
; CHECK-NOLSE-O1-NEXT: and w8, w8, #0xffff
3718+
; CHECK-NOLSE-O1-NEXT: cmp w8, w9
3719+
; CHECK-NOLSE-O1-NEXT: csel w10, w8, w9, lo
37203720
; CHECK-NOLSE-O1-NEXT: stlxrh w11, w10, [x0]
37213721
; CHECK-NOLSE-O1-NEXT: cbnz w11, LBB45_1
37223722
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3729,9 +3729,9 @@ define i16 @atomicrmw_umin_i16(ptr %ptr, i16 %rhs) {
37293729
; CHECK-OUTLINE-O1-NEXT: LBB45_1: ; %atomicrmw.start
37303730
; CHECK-OUTLINE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
37313731
; CHECK-OUTLINE-O1-NEXT: ldaxrh w8, [x0]
3732-
; CHECK-OUTLINE-O1-NEXT: and w10, w8, #0xffff
3733-
; CHECK-OUTLINE-O1-NEXT: cmp w10, w9
3734-
; CHECK-OUTLINE-O1-NEXT: csel w10, w10, w9, lo
3732+
; CHECK-OUTLINE-O1-NEXT: and w8, w8, #0xffff
3733+
; CHECK-OUTLINE-O1-NEXT: cmp w8, w9
3734+
; CHECK-OUTLINE-O1-NEXT: csel w10, w8, w9, lo
37353735
; CHECK-OUTLINE-O1-NEXT: stlxrh w11, w10, [x0]
37363736
; CHECK-OUTLINE-O1-NEXT: cbnz w11, LBB45_1
37373737
; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3836,9 +3836,9 @@ define i16 @atomicrmw_umax_i16(ptr %ptr, i16 %rhs) {
38363836
; CHECK-NOLSE-O1-NEXT: LBB46_1: ; %atomicrmw.start
38373837
; CHECK-NOLSE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
38383838
; CHECK-NOLSE-O1-NEXT: ldxrh w8, [x0]
3839-
; CHECK-NOLSE-O1-NEXT: and w10, w8, #0xffff
3840-
; CHECK-NOLSE-O1-NEXT: cmp w10, w9
3841-
; CHECK-NOLSE-O1-NEXT: csel w10, w10, w9, hi
3839+
; CHECK-NOLSE-O1-NEXT: and w8, w8, #0xffff
3840+
; CHECK-NOLSE-O1-NEXT: cmp w8, w9
3841+
; CHECK-NOLSE-O1-NEXT: csel w10, w8, w9, hi
38423842
; CHECK-NOLSE-O1-NEXT: stxrh w11, w10, [x0]
38433843
; CHECK-NOLSE-O1-NEXT: cbnz w11, LBB46_1
38443844
; CHECK-NOLSE-O1-NEXT: ; %bb.2: ; %atomicrmw.end
@@ -3851,9 +3851,9 @@ define i16 @atomicrmw_umax_i16(ptr %ptr, i16 %rhs) {
38513851
; CHECK-OUTLINE-O1-NEXT: LBB46_1: ; %atomicrmw.start
38523852
; CHECK-OUTLINE-O1-NEXT: ; =>This Inner Loop Header: Depth=1
38533853
; CHECK-OUTLINE-O1-NEXT: ldxrh w8, [x0]
3854-
; CHECK-OUTLINE-O1-NEXT: and w10, w8, #0xffff
3855-
; CHECK-OUTLINE-O1-NEXT: cmp w10, w9
3856-
; CHECK-OUTLINE-O1-NEXT: csel w10, w10, w9, hi
3854+
; CHECK-OUTLINE-O1-NEXT: and w8, w8, #0xffff
3855+
; CHECK-OUTLINE-O1-NEXT: cmp w8, w9
3856+
; CHECK-OUTLINE-O1-NEXT: csel w10, w8, w9, hi
38573857
; CHECK-OUTLINE-O1-NEXT: stxrh w11, w10, [x0]
38583858
; CHECK-OUTLINE-O1-NEXT: cbnz w11, LBB46_1
38593859
; CHECK-OUTLINE-O1-NEXT: ; %bb.2: ; %atomicrmw.end

‎llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll‎

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -926,16 +926,16 @@ define i8 @atomicrmw_umin_i8(ptr %ptr, i8 %rhs) {
926926
; CHECK-NEXT: liveins: $w9, $x0
927927
; CHECK-NEXT: {{ $}}
928928
; CHECK-NEXT: renamable $w8 = LDAXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s8) from %ir.ptr)
929-
; CHECK-NEXT: renamable $w10 = ANDWri renamable $w8, 7
930-
; CHECK-NEXT: $wzr = SUBSWrs renamable $w10, renamable $w9, 0, implicit-def $nzcv, pcsections !0
931-
; CHECK-NEXT: renamable $w10 = CSELWr killed renamable $w10, renamable $w9, 3, implicit killed $nzcv, implicit-def $x10, pcsections !0
929+
; CHECK-NEXT: renamable $w8 = ANDWri renamable $w8, 7, implicit killed $x8
930+
; CHECK-NEXT: $wzr = SUBSWrs renamable $w8, renamable $w9, 0, implicit-def $nzcv, pcsections !0
931+
; CHECK-NEXT: renamable $w10 = CSELWr renamable $w8, renamable $w9, 3, implicit killed $nzcv, implicit-def $x10, pcsections !0
932932
; CHECK-NEXT: early-clobber renamable $w11 = STLXRB renamable $w10, renamable $x0, implicit killed $x10, pcsections !0 :: (volatile store (s8) into %ir.ptr)
933933
; CHECK-NEXT: CBNZW killed renamable $w11, %bb.1, pcsections !0
934934
; CHECK-NEXT: {{ $}}
935935
; CHECK-NEXT: bb.2.atomicrmw.end:
936-
; CHECK-NEXT: liveins: $x8
936+
; CHECK-NEXT: liveins: $w8
937937
; CHECK-NEXT: {{ $}}
938-
; CHECK-NEXT: $w0 = ORRWrs $wzr, $w8, 0, implicit killed $x8
938+
; CHECK-NEXT: $w0 = ORRWrs $wzr, killed $w8, 0
939939
; CHECK-NEXT: RET undef $lr, implicit $w0
940940
%res = atomicrmw umin ptr %ptr, i8 %rhs seq_cst, !pcsections !0
941941
ret i8 %res
@@ -954,16 +954,16 @@ define i8 @atomicrmw_umax_i8(ptr %ptr, i8 %rhs) {
954954
; CHECK-NEXT: liveins: $w9, $x0
955955
; CHECK-NEXT: {{ $}}
956956
; CHECK-NEXT: renamable $w8 = LDXRB renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s8) from %ir.ptr)
957-
; CHECK-NEXT: renamable $w10 = ANDWri renamable $w8, 7
958-
; CHECK-NEXT: $wzr = SUBSWrs renamable $w10, renamable $w9, 0, implicit-def $nzcv, pcsections !0
959-
; CHECK-NEXT: renamable $w10 = CSELWr killed renamable $w10, renamable $w9, 8, implicit killed $nzcv, implicit-def $x10, pcsections !0
957+
; CHECK-NEXT: renamable $w8 = ANDWri renamable $w8, 7, implicit killed $x8
958+
; CHECK-NEXT: $wzr = SUBSWrs renamable $w8, renamable $w9, 0, implicit-def $nzcv, pcsections !0
959+
; CHECK-NEXT: renamable $w10 = CSELWr renamable $w8, renamable $w9, 8, implicit killed $nzcv, implicit-def $x10, pcsections !0
960960
; CHECK-NEXT: early-clobber renamable $w11 = STXRB renamable $w10, renamable $x0, implicit killed $x10, pcsections !0 :: (volatile store (s8) into %ir.ptr)
961961
; CHECK-NEXT: CBNZW killed renamable $w11, %bb.1, pcsections !0
962962
; CHECK-NEXT: {{ $}}
963963
; CHECK-NEXT: bb.2.atomicrmw.end:
964-
; CHECK-NEXT: liveins: $x8
964+
; CHECK-NEXT: liveins: $w8
965965
; CHECK-NEXT: {{ $}}
966-
; CHECK-NEXT: $w0 = ORRWrs $wzr, $w8, 0, implicit killed $x8
966+
; CHECK-NEXT: $w0 = ORRWrs $wzr, killed $w8, 0
967967
; CHECK-NEXT: RET undef $lr, implicit $w0
968968
%res = atomicrmw umax ptr %ptr, i8 %rhs monotonic, !pcsections !0
969969
ret i8 %res
@@ -1179,16 +1179,16 @@ define i16 @atomicrmw_umin_i16(ptr %ptr, i16 %rhs) {
11791179
; CHECK-NEXT: liveins: $w9, $x0
11801180
; CHECK-NEXT: {{ $}}
11811181
; CHECK-NEXT: renamable $w8 = LDAXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s16) from %ir.ptr)
1182-
; CHECK-NEXT: renamable $w10 = ANDWri renamable $w8, 15
1183-
; CHECK-NEXT: $wzr = SUBSWrs renamable $w10, renamable $w9, 0, implicit-def $nzcv, pcsections !0
1184-
; CHECK-NEXT: renamable $w10 = CSELWr killed renamable $w10, renamable $w9, 3, implicit killed $nzcv, implicit-def $x10, pcsections !0
1182+
; CHECK-NEXT: renamable $w8 = ANDWri renamable $w8, 15, implicit killed $x8
1183+
; CHECK-NEXT: $wzr = SUBSWrs renamable $w8, renamable $w9, 0, implicit-def $nzcv, pcsections !0
1184+
; CHECK-NEXT: renamable $w10 = CSELWr renamable $w8, renamable $w9, 3, implicit killed $nzcv, implicit-def $x10, pcsections !0
11851185
; CHECK-NEXT: early-clobber renamable $w11 = STLXRH renamable $w10, renamable $x0, implicit killed $x10, pcsections !0 :: (volatile store (s16) into %ir.ptr)
11861186
; CHECK-NEXT: CBNZW killed renamable $w11, %bb.1, pcsections !0
11871187
; CHECK-NEXT: {{ $}}
11881188
; CHECK-NEXT: bb.2.atomicrmw.end:
1189-
; CHECK-NEXT: liveins: $x8
1189+
; CHECK-NEXT: liveins: $w8
11901190
; CHECK-NEXT: {{ $}}
1191-
; CHECK-NEXT: $w0 = ORRWrs $wzr, $w8, 0, implicit killed $x8
1191+
; CHECK-NEXT: $w0 = ORRWrs $wzr, killed $w8, 0
11921192
; CHECK-NEXT: RET undef $lr, implicit $w0
11931193
%res = atomicrmw umin ptr %ptr, i16 %rhs seq_cst, !pcsections !0
11941194
ret i16 %res
@@ -1207,16 +1207,16 @@ define i16 @atomicrmw_umax_i16(ptr %ptr, i16 %rhs) {
12071207
; CHECK-NEXT: liveins: $w9, $x0
12081208
; CHECK-NEXT: {{ $}}
12091209
; CHECK-NEXT: renamable $w8 = LDXRH renamable $x0, implicit-def $x8, pcsections !0 :: (volatile load (s16) from %ir.ptr)
1210-
; CHECK-NEXT: renamable $w10 = ANDWri renamable $w8, 15
1211-
; CHECK-NEXT: $wzr = SUBSWrs renamable $w10, renamable $w9, 0, implicit-def $nzcv, pcsections !0
1212-
; CHECK-NEXT: renamable $w10 = CSELWr killed renamable $w10, renamable $w9, 8, implicit killed $nzcv, implicit-def $x10, pcsections !0
1210+
; CHECK-NEXT: renamable $w8 = ANDWri renamable $w8, 15, implicit killed $x8
1211+
; CHECK-NEXT: $wzr = SUBSWrs renamable $w8, renamable $w9, 0, implicit-def $nzcv, pcsections !0
1212+
; CHECK-NEXT: renamable $w10 = CSELWr renamable $w8, renamable $w9, 8, implicit killed $nzcv, implicit-def $x10, pcsections !0
12131213
; CHECK-NEXT: early-clobber renamable $w11 = STXRH renamable $w10, renamable $x0, implicit killed $x10, pcsections !0 :: (volatile store (s16) into %ir.ptr)
12141214
; CHECK-NEXT: CBNZW killed renamable $w11, %bb.1, pcsections !0
12151215
; CHECK-NEXT: {{ $}}
12161216
; CHECK-NEXT: bb.2.atomicrmw.end:
1217-
; CHECK-NEXT: liveins: $x8
1217+
; CHECK-NEXT: liveins: $w8
12181218
; CHECK-NEXT: {{ $}}
1219-
; CHECK-NEXT: $w0 = ORRWrs $wzr, $w8, 0, implicit killed $x8
1219+
; CHECK-NEXT: $w0 = ORRWrs $wzr, killed $w8, 0
12201220
; CHECK-NEXT: RET undef $lr, implicit $w0
12211221
%res = atomicrmw umax ptr %ptr, i16 %rhs monotonic, !pcsections !0
12221222
ret i16 %res

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