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[RISCV] Optimize VRELOAD/VSPILL lowering if VLEN is known. (#74421)
Instead of using VLENB and a shift, load (VLEN/8)*LMUL directly into a register. We could go further and use ADDI, but that would be more intrusive to the code structure. My primary goal is to remove the read of VLENB which might be expensive if it's not optimized in hardware.
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3 files changed

+260
-12
lines changed

3 files changed

+260
-12
lines changed

‎llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp‎

Lines changed: 28 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -299,12 +299,20 @@ void RISCVRegisterInfo::lowerVSPILL(MachineBasicBlock::iterator II) const {
299299
"Unexpected subreg numbering");
300300

301301
Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass);
302-
BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), VL);
303-
uint32_t ShiftAmount = Log2_32(LMUL);
304-
if (ShiftAmount != 0)
305-
BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL)
306-
.addReg(VL)
307-
.addImm(ShiftAmount);
302+
// Optimize for constant VLEN.
303+
const RISCVSubtarget &STI = MF.getSubtarget<RISCVSubtarget>();
304+
if (STI.getRealMinVLen() == STI.getRealMaxVLen()) {
305+
const int64_t VLENB = STI.getRealMinVLen() / 8;
306+
int64_t Offset = VLENB * LMUL;
307+
STI.getInstrInfo()->movImm(MBB, II, DL, VL, Offset);
308+
} else {
309+
BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), VL);
310+
uint32_t ShiftAmount = Log2_32(LMUL);
311+
if (ShiftAmount != 0)
312+
BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL)
313+
.addReg(VL)
314+
.addImm(ShiftAmount);
315+
}
308316

309317
Register SrcReg = II->getOperand(0).getReg();
310318
Register Base = II->getOperand(1).getReg();
@@ -368,12 +376,20 @@ void RISCVRegisterInfo::lowerVRELOAD(MachineBasicBlock::iterator II) const {
368376
"Unexpected subreg numbering");
369377

370378
Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass);
371-
BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), VL);
372-
uint32_t ShiftAmount = Log2_32(LMUL);
373-
if (ShiftAmount != 0)
374-
BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL)
375-
.addReg(VL)
376-
.addImm(ShiftAmount);
379+
// Optimize for constant VLEN.
380+
const RISCVSubtarget &STI = MF.getSubtarget<RISCVSubtarget>();
381+
if (STI.getRealMinVLen() == STI.getRealMaxVLen()) {
382+
const int64_t VLENB = STI.getRealMinVLen() / 8;
383+
int64_t Offset = VLENB * LMUL;
384+
STI.getInstrInfo()->movImm(MBB, II, DL, VL, Offset);
385+
} else {
386+
BuildMI(MBB, II, DL, TII->get(RISCV::PseudoReadVLENB), VL);
387+
uint32_t ShiftAmount = Log2_32(LMUL);
388+
if (ShiftAmount != 0)
389+
BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL)
390+
.addReg(VL)
391+
.addImm(ShiftAmount);
392+
}
377393

378394
Register DestReg = II->getOperand(0).getReg();
379395
Register Base = II->getOperand(1).getReg();

‎llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll‎

Lines changed: 116 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,8 @@
33
; RUN: | FileCheck --check-prefix=SPILL-O0 %s
44
; RUN: llc -mtriple=riscv32 -mattr=+v -mattr=+m -O2 < %s \
55
; RUN: | FileCheck --check-prefix=SPILL-O2 %s
6+
; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-max=128 -O2 < %s \
7+
; RUN: | FileCheck --check-prefix=SPILL-O2-VLEN128 %s
68

79
define <vscale x 1 x i32> @spill_zvlsseg_nxv1i32(ptr %base, i32 %vl) nounwind {
810
; SPILL-O0-LABEL: spill_zvlsseg_nxv1i32:
@@ -56,6 +58,28 @@ define <vscale x 1 x i32> @spill_zvlsseg_nxv1i32(ptr %base, i32 %vl) nounwind {
5658
; SPILL-O2-NEXT: add sp, sp, a0
5759
; SPILL-O2-NEXT: addi sp, sp, 16
5860
; SPILL-O2-NEXT: ret
61+
;
62+
; SPILL-O2-VLEN128-LABEL: spill_zvlsseg_nxv1i32:
63+
; SPILL-O2-VLEN128: # %bb.0: # %entry
64+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, -16
65+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, -32
66+
; SPILL-O2-VLEN128-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
67+
; SPILL-O2-VLEN128-NEXT: vlseg2e32.v v8, (a0)
68+
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
69+
; SPILL-O2-VLEN128-NEXT: li a1, 16
70+
; SPILL-O2-VLEN128-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
71+
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
72+
; SPILL-O2-VLEN128-NEXT: vs1r.v v9, (a0) # Unknown-size Folded Spill
73+
; SPILL-O2-VLEN128-NEXT: #APP
74+
; SPILL-O2-VLEN128-NEXT: #NO_APP
75+
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
76+
; SPILL-O2-VLEN128-NEXT: li a1, 16
77+
; SPILL-O2-VLEN128-NEXT: vl1r.v v7, (a0) # Unknown-size Folded Reload
78+
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
79+
; SPILL-O2-VLEN128-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
80+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 32
81+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 16
82+
; SPILL-O2-VLEN128-NEXT: ret
5983
entry:
6084
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i32 %vl)
6185
call void asm sideeffect "",
@@ -116,6 +140,28 @@ define <vscale x 2 x i32> @spill_zvlsseg_nxv2i32(ptr %base, i32 %vl) nounwind {
116140
; SPILL-O2-NEXT: add sp, sp, a0
117141
; SPILL-O2-NEXT: addi sp, sp, 16
118142
; SPILL-O2-NEXT: ret
143+
;
144+
; SPILL-O2-VLEN128-LABEL: spill_zvlsseg_nxv2i32:
145+
; SPILL-O2-VLEN128: # %bb.0: # %entry
146+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, -16
147+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, -32
148+
; SPILL-O2-VLEN128-NEXT: vsetvli zero, a1, e32, m1, ta, ma
149+
; SPILL-O2-VLEN128-NEXT: vlseg2e32.v v8, (a0)
150+
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
151+
; SPILL-O2-VLEN128-NEXT: li a1, 16
152+
; SPILL-O2-VLEN128-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
153+
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
154+
; SPILL-O2-VLEN128-NEXT: vs1r.v v9, (a0) # Unknown-size Folded Spill
155+
; SPILL-O2-VLEN128-NEXT: #APP
156+
; SPILL-O2-VLEN128-NEXT: #NO_APP
157+
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
158+
; SPILL-O2-VLEN128-NEXT: li a1, 16
159+
; SPILL-O2-VLEN128-NEXT: vl1r.v v7, (a0) # Unknown-size Folded Reload
160+
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
161+
; SPILL-O2-VLEN128-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
162+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 32
163+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 16
164+
; SPILL-O2-VLEN128-NEXT: ret
119165
entry:
120166
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg2.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, ptr %base, i32 %vl)
121167
call void asm sideeffect "",
@@ -179,6 +225,28 @@ define <vscale x 4 x i32> @spill_zvlsseg_nxv4i32(ptr %base, i32 %vl) nounwind {
179225
; SPILL-O2-NEXT: add sp, sp, a0
180226
; SPILL-O2-NEXT: addi sp, sp, 16
181227
; SPILL-O2-NEXT: ret
228+
;
229+
; SPILL-O2-VLEN128-LABEL: spill_zvlsseg_nxv4i32:
230+
; SPILL-O2-VLEN128: # %bb.0: # %entry
231+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, -16
232+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, -64
233+
; SPILL-O2-VLEN128-NEXT: vsetvli zero, a1, e32, m2, ta, ma
234+
; SPILL-O2-VLEN128-NEXT: vlseg2e32.v v8, (a0)
235+
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
236+
; SPILL-O2-VLEN128-NEXT: li a1, 32
237+
; SPILL-O2-VLEN128-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill
238+
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
239+
; SPILL-O2-VLEN128-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill
240+
; SPILL-O2-VLEN128-NEXT: #APP
241+
; SPILL-O2-VLEN128-NEXT: #NO_APP
242+
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
243+
; SPILL-O2-VLEN128-NEXT: li a1, 32
244+
; SPILL-O2-VLEN128-NEXT: vl2r.v v6, (a0) # Unknown-size Folded Reload
245+
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
246+
; SPILL-O2-VLEN128-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload
247+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 64
248+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 16
249+
; SPILL-O2-VLEN128-NEXT: ret
182250
entry:
183251
%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg2.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, ptr %base, i32 %vl)
184252
call void asm sideeffect "",
@@ -242,6 +310,28 @@ define <vscale x 8 x i32> @spill_zvlsseg_nxv8i32(ptr %base, i32 %vl) nounwind {
242310
; SPILL-O2-NEXT: add sp, sp, a0
243311
; SPILL-O2-NEXT: addi sp, sp, 16
244312
; SPILL-O2-NEXT: ret
313+
;
314+
; SPILL-O2-VLEN128-LABEL: spill_zvlsseg_nxv8i32:
315+
; SPILL-O2-VLEN128: # %bb.0: # %entry
316+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, -16
317+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, -128
318+
; SPILL-O2-VLEN128-NEXT: vsetvli zero, a1, e32, m4, ta, ma
319+
; SPILL-O2-VLEN128-NEXT: vlseg2e32.v v8, (a0)
320+
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
321+
; SPILL-O2-VLEN128-NEXT: li a1, 64
322+
; SPILL-O2-VLEN128-NEXT: vs4r.v v8, (a0) # Unknown-size Folded Spill
323+
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
324+
; SPILL-O2-VLEN128-NEXT: vs4r.v v12, (a0) # Unknown-size Folded Spill
325+
; SPILL-O2-VLEN128-NEXT: #APP
326+
; SPILL-O2-VLEN128-NEXT: #NO_APP
327+
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
328+
; SPILL-O2-VLEN128-NEXT: li a1, 64
329+
; SPILL-O2-VLEN128-NEXT: vl4r.v v4, (a0) # Unknown-size Folded Reload
330+
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
331+
; SPILL-O2-VLEN128-NEXT: vl4r.v v8, (a0) # Unknown-size Folded Reload
332+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 128
333+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 16
334+
; SPILL-O2-VLEN128-NEXT: ret
245335
entry:
246336
%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlseg2.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef, ptr %base, i32 %vl)
247337
call void asm sideeffect "",
@@ -314,6 +404,32 @@ define <vscale x 4 x i32> @spill_zvlsseg3_nxv4i32(ptr %base, i32 %vl) nounwind {
314404
; SPILL-O2-NEXT: add sp, sp, a0
315405
; SPILL-O2-NEXT: addi sp, sp, 16
316406
; SPILL-O2-NEXT: ret
407+
;
408+
; SPILL-O2-VLEN128-LABEL: spill_zvlsseg3_nxv4i32:
409+
; SPILL-O2-VLEN128: # %bb.0: # %entry
410+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, -16
411+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, -96
412+
; SPILL-O2-VLEN128-NEXT: vsetvli zero, a1, e32, m2, ta, ma
413+
; SPILL-O2-VLEN128-NEXT: vlseg3e32.v v8, (a0)
414+
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
415+
; SPILL-O2-VLEN128-NEXT: li a1, 32
416+
; SPILL-O2-VLEN128-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill
417+
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
418+
; SPILL-O2-VLEN128-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill
419+
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
420+
; SPILL-O2-VLEN128-NEXT: vs2r.v v12, (a0) # Unknown-size Folded Spill
421+
; SPILL-O2-VLEN128-NEXT: #APP
422+
; SPILL-O2-VLEN128-NEXT: #NO_APP
423+
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
424+
; SPILL-O2-VLEN128-NEXT: li a1, 32
425+
; SPILL-O2-VLEN128-NEXT: vl2r.v v6, (a0) # Unknown-size Folded Reload
426+
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
427+
; SPILL-O2-VLEN128-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload
428+
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
429+
; SPILL-O2-VLEN128-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
430+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 96
431+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 16
432+
; SPILL-O2-VLEN128-NEXT: ret
317433
entry:
318434
%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg3.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, ptr %base, i32 %vl)
319435
call void asm sideeffect "",

‎llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll‎

Lines changed: 116 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,8 @@
33
; RUN: | FileCheck --check-prefix=SPILL-O0 %s
44
; RUN: llc -mtriple=riscv64 -mattr=+v -mattr=+m -O2 < %s \
55
; RUN: | FileCheck --check-prefix=SPILL-O2 %s
6+
; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-max=128 -O2 < %s \
7+
; RUN: | FileCheck --check-prefix=SPILL-O2-VLEN128 %s
68

79
define <vscale x 1 x i32> @spill_zvlsseg_nxv1i32(ptr %base, i64 %vl) nounwind {
810
; SPILL-O0-LABEL: spill_zvlsseg_nxv1i32:
@@ -56,6 +58,28 @@ define <vscale x 1 x i32> @spill_zvlsseg_nxv1i32(ptr %base, i64 %vl) nounwind {
5658
; SPILL-O2-NEXT: add sp, sp, a0
5759
; SPILL-O2-NEXT: addi sp, sp, 16
5860
; SPILL-O2-NEXT: ret
61+
;
62+
; SPILL-O2-VLEN128-LABEL: spill_zvlsseg_nxv1i32:
63+
; SPILL-O2-VLEN128: # %bb.0: # %entry
64+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, -16
65+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, -32
66+
; SPILL-O2-VLEN128-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
67+
; SPILL-O2-VLEN128-NEXT: vlseg2e32.v v8, (a0)
68+
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
69+
; SPILL-O2-VLEN128-NEXT: li a1, 16
70+
; SPILL-O2-VLEN128-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
71+
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
72+
; SPILL-O2-VLEN128-NEXT: vs1r.v v9, (a0) # Unknown-size Folded Spill
73+
; SPILL-O2-VLEN128-NEXT: #APP
74+
; SPILL-O2-VLEN128-NEXT: #NO_APP
75+
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
76+
; SPILL-O2-VLEN128-NEXT: li a1, 16
77+
; SPILL-O2-VLEN128-NEXT: vl1r.v v7, (a0) # Unknown-size Folded Reload
78+
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
79+
; SPILL-O2-VLEN128-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
80+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 32
81+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 16
82+
; SPILL-O2-VLEN128-NEXT: ret
5983
entry:
6084
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>} @llvm.riscv.vlseg2.nxv1i32(<vscale x 1 x i32> undef, <vscale x 1 x i32> undef, ptr %base, i64 %vl)
6185
call void asm sideeffect "",
@@ -116,6 +140,28 @@ define <vscale x 2 x i32> @spill_zvlsseg_nxv2i32(ptr %base, i64 %vl) nounwind {
116140
; SPILL-O2-NEXT: add sp, sp, a0
117141
; SPILL-O2-NEXT: addi sp, sp, 16
118142
; SPILL-O2-NEXT: ret
143+
;
144+
; SPILL-O2-VLEN128-LABEL: spill_zvlsseg_nxv2i32:
145+
; SPILL-O2-VLEN128: # %bb.0: # %entry
146+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, -16
147+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, -32
148+
; SPILL-O2-VLEN128-NEXT: vsetvli zero, a1, e32, m1, ta, ma
149+
; SPILL-O2-VLEN128-NEXT: vlseg2e32.v v8, (a0)
150+
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
151+
; SPILL-O2-VLEN128-NEXT: li a1, 16
152+
; SPILL-O2-VLEN128-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
153+
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
154+
; SPILL-O2-VLEN128-NEXT: vs1r.v v9, (a0) # Unknown-size Folded Spill
155+
; SPILL-O2-VLEN128-NEXT: #APP
156+
; SPILL-O2-VLEN128-NEXT: #NO_APP
157+
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
158+
; SPILL-O2-VLEN128-NEXT: li a1, 16
159+
; SPILL-O2-VLEN128-NEXT: vl1r.v v7, (a0) # Unknown-size Folded Reload
160+
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
161+
; SPILL-O2-VLEN128-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
162+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 32
163+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 16
164+
; SPILL-O2-VLEN128-NEXT: ret
119165
entry:
120166
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>} @llvm.riscv.vlseg2.nxv2i32(<vscale x 2 x i32> undef, <vscale x 2 x i32> undef, ptr %base, i64 %vl)
121167
call void asm sideeffect "",
@@ -179,6 +225,28 @@ define <vscale x 4 x i32> @spill_zvlsseg_nxv4i32(ptr %base, i64 %vl) nounwind {
179225
; SPILL-O2-NEXT: add sp, sp, a0
180226
; SPILL-O2-NEXT: addi sp, sp, 16
181227
; SPILL-O2-NEXT: ret
228+
;
229+
; SPILL-O2-VLEN128-LABEL: spill_zvlsseg_nxv4i32:
230+
; SPILL-O2-VLEN128: # %bb.0: # %entry
231+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, -16
232+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, -64
233+
; SPILL-O2-VLEN128-NEXT: vsetvli zero, a1, e32, m2, ta, ma
234+
; SPILL-O2-VLEN128-NEXT: vlseg2e32.v v8, (a0)
235+
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
236+
; SPILL-O2-VLEN128-NEXT: li a1, 32
237+
; SPILL-O2-VLEN128-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill
238+
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
239+
; SPILL-O2-VLEN128-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill
240+
; SPILL-O2-VLEN128-NEXT: #APP
241+
; SPILL-O2-VLEN128-NEXT: #NO_APP
242+
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
243+
; SPILL-O2-VLEN128-NEXT: li a1, 32
244+
; SPILL-O2-VLEN128-NEXT: vl2r.v v6, (a0) # Unknown-size Folded Reload
245+
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
246+
; SPILL-O2-VLEN128-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload
247+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 64
248+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 16
249+
; SPILL-O2-VLEN128-NEXT: ret
182250
entry:
183251
%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg2.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, ptr %base, i64 %vl)
184252
call void asm sideeffect "",
@@ -242,6 +310,28 @@ define <vscale x 8 x i32> @spill_zvlsseg_nxv8i32(ptr %base, i64 %vl) nounwind {
242310
; SPILL-O2-NEXT: add sp, sp, a0
243311
; SPILL-O2-NEXT: addi sp, sp, 16
244312
; SPILL-O2-NEXT: ret
313+
;
314+
; SPILL-O2-VLEN128-LABEL: spill_zvlsseg_nxv8i32:
315+
; SPILL-O2-VLEN128: # %bb.0: # %entry
316+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, -16
317+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, -128
318+
; SPILL-O2-VLEN128-NEXT: vsetvli zero, a1, e32, m4, ta, ma
319+
; SPILL-O2-VLEN128-NEXT: vlseg2e32.v v8, (a0)
320+
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
321+
; SPILL-O2-VLEN128-NEXT: li a1, 64
322+
; SPILL-O2-VLEN128-NEXT: vs4r.v v8, (a0) # Unknown-size Folded Spill
323+
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
324+
; SPILL-O2-VLEN128-NEXT: vs4r.v v12, (a0) # Unknown-size Folded Spill
325+
; SPILL-O2-VLEN128-NEXT: #APP
326+
; SPILL-O2-VLEN128-NEXT: #NO_APP
327+
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
328+
; SPILL-O2-VLEN128-NEXT: li a1, 64
329+
; SPILL-O2-VLEN128-NEXT: vl4r.v v4, (a0) # Unknown-size Folded Reload
330+
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
331+
; SPILL-O2-VLEN128-NEXT: vl4r.v v8, (a0) # Unknown-size Folded Reload
332+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 128
333+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 16
334+
; SPILL-O2-VLEN128-NEXT: ret
245335
entry:
246336
%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>} @llvm.riscv.vlseg2.nxv8i32(<vscale x 8 x i32> undef, <vscale x 8 x i32> undef, ptr %base, i64 %vl)
247337
call void asm sideeffect "",
@@ -314,6 +404,32 @@ define <vscale x 4 x i32> @spill_zvlsseg3_nxv4i32(ptr %base, i64 %vl) nounwind {
314404
; SPILL-O2-NEXT: add sp, sp, a0
315405
; SPILL-O2-NEXT: addi sp, sp, 16
316406
; SPILL-O2-NEXT: ret
407+
;
408+
; SPILL-O2-VLEN128-LABEL: spill_zvlsseg3_nxv4i32:
409+
; SPILL-O2-VLEN128: # %bb.0: # %entry
410+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, -16
411+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, -96
412+
; SPILL-O2-VLEN128-NEXT: vsetvli zero, a1, e32, m2, ta, ma
413+
; SPILL-O2-VLEN128-NEXT: vlseg3e32.v v8, (a0)
414+
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
415+
; SPILL-O2-VLEN128-NEXT: li a1, 32
416+
; SPILL-O2-VLEN128-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill
417+
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
418+
; SPILL-O2-VLEN128-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill
419+
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
420+
; SPILL-O2-VLEN128-NEXT: vs2r.v v12, (a0) # Unknown-size Folded Spill
421+
; SPILL-O2-VLEN128-NEXT: #APP
422+
; SPILL-O2-VLEN128-NEXT: #NO_APP
423+
; SPILL-O2-VLEN128-NEXT: addi a0, sp, 16
424+
; SPILL-O2-VLEN128-NEXT: li a1, 32
425+
; SPILL-O2-VLEN128-NEXT: vl2r.v v6, (a0) # Unknown-size Folded Reload
426+
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
427+
; SPILL-O2-VLEN128-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload
428+
; SPILL-O2-VLEN128-NEXT: add a0, a0, a1
429+
; SPILL-O2-VLEN128-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
430+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 96
431+
; SPILL-O2-VLEN128-NEXT: addi sp, sp, 16
432+
; SPILL-O2-VLEN128-NEXT: ret
317433
entry:
318434
%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>} @llvm.riscv.vlseg3.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i32> undef, <vscale x 4 x i32> undef, ptr %base, i64 %vl)
319435
call void asm sideeffect "",

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