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[InstCombine][X86] Add vpermilpd/vpermilps test coverage for #106413 
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‎llvm/test/Transforms/InstCombine/X86/x86-vpermil-inseltpoison.ll‎

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Original file line numberDiff line numberDiff line change
@@ -221,6 +221,86 @@ define <8 x double> @poison_test_vpermilvar_pd_512(<8 x double> %v) {
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ret <8 x double> %a
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}
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; Simplify demanded bits (PR106413)
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define <4 x float> @bits_test_vpermilvar_ps(<4 x float> %InVec, <4 x i32> %InMask) {
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; CHECK-LABEL: @bits_test_vpermilvar_ps(
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; CHECK-NEXT: [[M:%.*]] = or <4 x i32> [[INMASK:%.*]], <i32 0, i32 12, i32 -4, i32 -4>
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; CHECK-NEXT: [[S:%.*]] = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> [[INVEC:%.*]], <4 x i32> [[M]])
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; CHECK-NEXT: ret <4 x float> [[S]]
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;
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%m = or <4 x i32> %InMask, <i32 0, i32 12, i32 4294967292, i32 -4>
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%s = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %InVec, <4 x i32> %m)
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ret <4 x float> %s
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}
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define <8 x float> @bits_test_vpermilvar_ps_256(<8 x float> %InVec, <8 x i32> %InMask) {
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; CHECK-LABEL: @bits_test_vpermilvar_ps_256(
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; CHECK-NEXT: [[M:%.*]] = or <8 x i32> [[INMASK:%.*]], <i32 0, i32 12, i32 -4, i32 -4, i32 0, i32 12, i32 -4, i32 -4>
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; CHECK-NEXT: [[S:%.*]] = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> [[INVEC:%.*]], <8 x i32> [[M]])
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; CHECK-NEXT: ret <8 x float> [[S]]
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;
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%m = or <8 x i32> %InMask, <i32 0, i32 12, i32 4294967292, i32 -4, i32 0, i32 12, i32 4294967292, i32 -4>
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%s = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %InVec, <8 x i32> %m)
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ret <8 x float> %s
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}
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define <16 x float> @bits_test_vpermilvar_ps_512(<16 x float> %InVec, <16 x i32> %InMask) {
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; CHECK-LABEL: @bits_test_vpermilvar_ps_512(
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; CHECK-NEXT: [[M:%.*]] = or <16 x i32> [[INMASK:%.*]], <i32 0, i32 12, i32 -4, i32 -4, i32 0, i32 12, i32 -4, i32 -4, i32 0, i32 12, i32 -4, i32 -4, i32 0, i32 12, i32 -4, i32 -4>
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; CHECK-NEXT: [[S:%.*]] = tail call <16 x float> @llvm.x86.avx512.vpermilvar.ps.512(<16 x float> [[INVEC:%.*]], <16 x i32> [[M]])
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; CHECK-NEXT: ret <16 x float> [[S]]
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;
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%m = or <16 x i32> %InMask, <i32 0, i32 12, i32 4294967292, i32 -4, i32 0, i32 12, i32 4294967292, i32 -4, i32 0, i32 12, i32 4294967292, i32 -4, i32 0, i32 12, i32 4294967292, i32 -4>
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%s = tail call <16 x float> @llvm.x86.avx512.vpermilvar.ps.512(<16 x float> %InVec, <16 x i32> %m)
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ret <16 x float> %s
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}
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define <2 x double> @bits_test_vpermilvar_pd(<2 x double> %InVec, <2 x i64> %InMask) {
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; CHECK-LABEL: @bits_test_vpermilvar_pd(
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; CHECK-NEXT: [[M:%.*]] = or <2 x i64> [[INMASK:%.*]], <i64 0, i64 4294967293>
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; CHECK-NEXT: [[S:%.*]] = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> [[INVEC:%.*]], <2 x i64> [[M]])
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; CHECK-NEXT: ret <2 x double> [[S]]
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;
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%m = or <2 x i64> %InMask, <i64 0, i64 4294967293>
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%s = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %InVec, <2 x i64> %m)
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ret <2 x double> %s
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}
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define <4 x double> @bits_test_vpermilvar_pd_256(<4 x double> %InVec, <4 x i64> %InMask) {
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; CHECK-LABEL: @bits_test_vpermilvar_pd_256(
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; CHECK-NEXT: [[M:%.*]] = or <4 x i64> [[INMASK:%.*]], <i64 0, i64 1, i64 4294967293, i64 -3>
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; CHECK-NEXT: [[S:%.*]] = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> [[INVEC:%.*]], <4 x i64> [[M]])
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; CHECK-NEXT: ret <4 x double> [[S]]
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;
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%m = or <4 x i64> %InMask, <i64 0, i64 1, i64 4294967293, i64 -3>
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%s = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %InVec, <4 x i64> %m)
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ret <4 x double> %s
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}
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define <8 x double> @bits_test_vpermilvar_pd_512(<8 x double> %InVec, <8 x i64> %InMask) {
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; CHECK-LABEL: @bits_test_vpermilvar_pd_512(
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; CHECK-NEXT: [[M:%.*]] = or <8 x i64> [[INMASK:%.*]], <i64 0, i64 1, i64 4294967293, i64 -3, i64 0, i64 1, i64 4294967293, i64 -3>
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; CHECK-NEXT: [[S:%.*]] = tail call <8 x double> @llvm.x86.avx512.vpermilvar.pd.512(<8 x double> [[INVEC:%.*]], <8 x i64> [[M]])
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; CHECK-NEXT: ret <8 x double> [[S]]
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;
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%m = or <8 x i64> %InMask, <i64 0, i64 1, i64 4294967293, i64 -3, i64 0, i64 1, i64 4294967293, i64 -3>
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%s = tail call <8 x double> @llvm.x86.avx512.vpermilvar.pd.512(<8 x double> %InVec, <8 x i64> %m)
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ret <8 x double> %s
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}
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; negative test - vpermilpd uses bit1 not bit0 for the index bit
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define <2 x double> @bits_test_vpermilvar_pd_negative(<2 x double> %InVec, <2 x i64> %InMask) {
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; CHECK-LABEL: @bits_test_vpermilvar_pd_negative(
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; CHECK-NEXT: [[M:%.*]] = or <2 x i64> [[INMASK:%.*]], <i64 0, i64 2>
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; CHECK-NEXT: [[S:%.*]] = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> [[INVEC:%.*]], <2 x i64> [[M]])
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; CHECK-NEXT: ret <2 x double> [[S]]
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;
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%m = or <2 x i64> %InMask, <i64 0, i64 2>
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%s = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %InVec, <2 x i64> %m)
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ret <2 x double> %s
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}
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; Simplify demanded elts
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define <4 x float> @elts_test_vpermilvar_ps(<4 x float> %a0, i32 %a1) {

‎llvm/test/Transforms/InstCombine/X86/x86-vpermil.ll‎

Lines changed: 80 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -221,6 +221,86 @@ define <8 x double> @undef_test_vpermilvar_pd_512(<8 x double> %v) {
221221
ret <8 x double> %a
222222
}
223223

224+
; Simplify demanded bits (PR106413)
225+
226+
define <4 x float> @bits_test_vpermilvar_ps(<4 x float> %InVec, <4 x i32> %InMask) {
227+
; CHECK-LABEL: @bits_test_vpermilvar_ps(
228+
; CHECK-NEXT: [[M:%.*]] = or <4 x i32> [[INMASK:%.*]], <i32 0, i32 12, i32 -4, i32 -4>
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; CHECK-NEXT: [[S:%.*]] = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> [[INVEC:%.*]], <4 x i32> [[M]])
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; CHECK-NEXT: ret <4 x float> [[S]]
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;
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%m = or <4 x i32> %InMask, <i32 0, i32 12, i32 4294967292, i32 -4>
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%s = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %InVec, <4 x i32> %m)
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ret <4 x float> %s
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}
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define <8 x float> @bits_test_vpermilvar_ps_256(<8 x float> %InVec, <8 x i32> %InMask) {
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; CHECK-LABEL: @bits_test_vpermilvar_ps_256(
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; CHECK-NEXT: [[M:%.*]] = or <8 x i32> [[INMASK:%.*]], <i32 0, i32 12, i32 -4, i32 -4, i32 0, i32 12, i32 -4, i32 -4>
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; CHECK-NEXT: [[S:%.*]] = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> [[INVEC:%.*]], <8 x i32> [[M]])
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; CHECK-NEXT: ret <8 x float> [[S]]
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;
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%m = or <8 x i32> %InMask, <i32 0, i32 12, i32 4294967292, i32 -4, i32 0, i32 12, i32 4294967292, i32 -4>
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%s = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %InVec, <8 x i32> %m)
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ret <8 x float> %s
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}
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define <16 x float> @bits_test_vpermilvar_ps_512(<16 x float> %InVec, <16 x i32> %InMask) {
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; CHECK-LABEL: @bits_test_vpermilvar_ps_512(
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; CHECK-NEXT: [[M:%.*]] = or <16 x i32> [[INMASK:%.*]], <i32 0, i32 12, i32 -4, i32 -4, i32 0, i32 12, i32 -4, i32 -4, i32 0, i32 12, i32 -4, i32 -4, i32 0, i32 12, i32 -4, i32 -4>
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; CHECK-NEXT: [[S:%.*]] = tail call <16 x float> @llvm.x86.avx512.vpermilvar.ps.512(<16 x float> [[INVEC:%.*]], <16 x i32> [[M]])
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; CHECK-NEXT: ret <16 x float> [[S]]
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;
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%m = or <16 x i32> %InMask, <i32 0, i32 12, i32 4294967292, i32 -4, i32 0, i32 12, i32 4294967292, i32 -4, i32 0, i32 12, i32 4294967292, i32 -4, i32 0, i32 12, i32 4294967292, i32 -4>
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%s = tail call <16 x float> @llvm.x86.avx512.vpermilvar.ps.512(<16 x float> %InVec, <16 x i32> %m)
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ret <16 x float> %s
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}
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define <2 x double> @bits_test_vpermilvar_pd(<2 x double> %InVec, <2 x i64> %InMask) {
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; CHECK-LABEL: @bits_test_vpermilvar_pd(
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; CHECK-NEXT: [[M:%.*]] = or <2 x i64> [[INMASK:%.*]], <i64 0, i64 4294967293>
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; CHECK-NEXT: [[S:%.*]] = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> [[INVEC:%.*]], <2 x i64> [[M]])
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; CHECK-NEXT: ret <2 x double> [[S]]
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;
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%m = or <2 x i64> %InMask, <i64 0, i64 4294967293>
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%s = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %InVec, <2 x i64> %m)
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ret <2 x double> %s
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}
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define <4 x double> @bits_test_vpermilvar_pd_256(<4 x double> %InVec, <4 x i64> %InMask) {
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; CHECK-LABEL: @bits_test_vpermilvar_pd_256(
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; CHECK-NEXT: [[M:%.*]] = or <4 x i64> [[INMASK:%.*]], <i64 0, i64 1, i64 4294967293, i64 -3>
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; CHECK-NEXT: [[S:%.*]] = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> [[INVEC:%.*]], <4 x i64> [[M]])
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; CHECK-NEXT: ret <4 x double> [[S]]
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;
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%m = or <4 x i64> %InMask, <i64 0, i64 1, i64 4294967293, i64 -3>
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%s = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %InVec, <4 x i64> %m)
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ret <4 x double> %s
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}
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define <8 x double> @bits_test_vpermilvar_pd_512(<8 x double> %InVec, <8 x i64> %InMask) {
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; CHECK-LABEL: @bits_test_vpermilvar_pd_512(
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; CHECK-NEXT: [[M:%.*]] = or <8 x i64> [[INMASK:%.*]], <i64 0, i64 1, i64 4294967293, i64 -3, i64 0, i64 1, i64 4294967293, i64 -3>
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; CHECK-NEXT: [[S:%.*]] = tail call <8 x double> @llvm.x86.avx512.vpermilvar.pd.512(<8 x double> [[INVEC:%.*]], <8 x i64> [[M]])
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; CHECK-NEXT: ret <8 x double> [[S]]
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;
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%m = or <8 x i64> %InMask, <i64 0, i64 1, i64 4294967293, i64 -3, i64 0, i64 1, i64 4294967293, i64 -3>
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%s = tail call <8 x double> @llvm.x86.avx512.vpermilvar.pd.512(<8 x double> %InVec, <8 x i64> %m)
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ret <8 x double> %s
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}
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; negative test - vpermilpd uses bit1 not bit0 for the index bit
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define <2 x double> @bits_test_vpermilvar_pd_negative(<2 x double> %InVec, <2 x i64> %InMask) {
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; CHECK-LABEL: @bits_test_vpermilvar_pd_negative(
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; CHECK-NEXT: [[M:%.*]] = or <2 x i64> [[INMASK:%.*]], <i64 0, i64 2>
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; CHECK-NEXT: [[S:%.*]] = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> [[INVEC:%.*]], <2 x i64> [[M]])
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; CHECK-NEXT: ret <2 x double> [[S]]
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;
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%m = or <2 x i64> %InMask, <i64 0, i64 2>
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%s = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %InVec, <2 x i64> %m)
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ret <2 x double> %s
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}
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224304
; Simplify demanded elts
225305

226306
define <4 x float> @elts_test_vpermilvar_ps(<4 x float> %a0, i32 %a1) {

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