44target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
55
66; FIXME: Currently the operands of %l are incorrectly truncated.
7- define void @test_pr47927_const_shift_ops (ptr %dst , i32 %f ) {
8- ; CHECK-LABEL: define void @test_pr47927_const_shift_ops
7+ define void @test_pr47927_lshr_const_shift_ops (ptr %dst , i32 %f ) {
8+ ; CHECK-LABEL: define void @test_pr47927_lshr_const_shift_ops
99; CHECK-SAME: (ptr [[DST:%.*]], i32 [[F:%.*]]) {
1010; CHECK-NEXT: entry:
1111; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
@@ -67,6 +67,132 @@ exit:
6767 ret void
6868}
6969
70+ define void @test_shl_const_shift_ops (ptr %dst , i32 %f ) {
71+ ; CHECK-LABEL: define void @test_shl_const_shift_ops
72+ ; CHECK-SAME: (ptr [[DST:%.*]], i32 [[F:%.*]]) {
73+ ; CHECK-NEXT: entry:
74+ ; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
75+ ; CHECK: vector.ph:
76+ ; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[F]], i64 0
77+ ; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer
78+ ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
79+ ; CHECK: vector.body:
80+ ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
81+ ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = trunc i32 [[INDEX]] to i8
82+ ; CHECK-NEXT: [[TMP0:%.*]] = add i8 [[OFFSET_IDX]], 0
83+ ; CHECK-NEXT: [[TMP1:%.*]] = trunc <4 x i32> [[BROADCAST_SPLAT]] to <4 x i8>
84+ ; CHECK-NEXT: [[TMP2:%.*]] = shl <4 x i8> [[TMP1]], <i8 18, i8 18, i8 18, i8 18>
85+ ; CHECK-NEXT: [[TMP3:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i32>
86+ ; CHECK-NEXT: [[TMP4:%.*]] = trunc <4 x i32> [[TMP3]] to <4 x i8>
87+ ; CHECK-NEXT: [[TMP5:%.*]] = zext i8 [[TMP0]] to i64
88+ ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[TMP5]]
89+ ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[TMP6]], i32 0
90+ ; CHECK-NEXT: store <4 x i8> [[TMP4]], ptr [[TMP7]], align 8
91+ ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
92+ ; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i32 [[INDEX_NEXT]], 100
93+ ; CHECK-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
94+ ; CHECK: middle.block:
95+ ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 100, 100
96+ ; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
97+ ; CHECK: scalar.ph:
98+ ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i8 [ 100, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
99+ ; CHECK-NEXT: br label [[LOOP:%.*]]
100+ ; CHECK: loop:
101+ ; CHECK-NEXT: [[IV:%.*]] = phi i8 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
102+ ; CHECK-NEXT: [[L:%.*]] = shl i32 [[F]], 18
103+ ; CHECK-NEXT: [[L_T:%.*]] = trunc i32 [[L]] to i8
104+ ; CHECK-NEXT: [[IV_EXT:%.*]] = zext i8 [[IV]] to i64
105+ ; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[IV_EXT]]
106+ ; CHECK-NEXT: store i8 [[L_T]], ptr [[GEP]], align 8
107+ ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
108+ ; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[IV_NEXT]] to i32
109+ ; CHECK-NEXT: [[C:%.*]] = icmp ne i32 [[CONV]], 100
110+ ; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP5:![0-9]+]]
111+ ; CHECK: exit:
112+ ; CHECK-NEXT: ret void
113+ ;
114+ entry:
115+ br label %loop
116+
117+ loop:
118+ %iv = phi i8 [ 0 , %entry ], [ %iv.next , %loop ]
119+ %l = shl i32 %f , 18
120+ %l.t = trunc i32 %l to i8
121+ %iv.ext = zext i8 %iv to i64
122+ %gep = getelementptr inbounds i8 , ptr %dst , i64 %iv.ext
123+ store i8 %l.t , ptr %gep , align 8
124+ %iv.next = add i8 %iv , 1
125+ %conv = zext i8 %iv.next to i32
126+ %c = icmp ne i32 %conv , 100
127+ br i1 %c , label %loop , label %exit
128+
129+ exit:
130+ ret void
131+ }
132+
133+ define void @test_ashr_const_shift_ops (ptr %dst , i32 %f ) {
134+ ; CHECK-LABEL: define void @test_ashr_const_shift_ops
135+ ; CHECK-SAME: (ptr [[DST:%.*]], i32 [[F:%.*]]) {
136+ ; CHECK-NEXT: entry:
137+ ; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
138+ ; CHECK: vector.ph:
139+ ; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[F]], i64 0
140+ ; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer
141+ ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
142+ ; CHECK: vector.body:
143+ ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
144+ ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = trunc i32 [[INDEX]] to i8
145+ ; CHECK-NEXT: [[TMP0:%.*]] = add i8 [[OFFSET_IDX]], 0
146+ ; CHECK-NEXT: [[TMP1:%.*]] = trunc <4 x i32> [[BROADCAST_SPLAT]] to <4 x i8>
147+ ; CHECK-NEXT: [[TMP2:%.*]] = ashr <4 x i8> [[TMP1]], <i8 18, i8 18, i8 18, i8 18>
148+ ; CHECK-NEXT: [[TMP3:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i32>
149+ ; CHECK-NEXT: [[TMP4:%.*]] = trunc <4 x i32> [[TMP3]] to <4 x i8>
150+ ; CHECK-NEXT: [[TMP5:%.*]] = zext i8 [[TMP0]] to i64
151+ ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[TMP5]]
152+ ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i8, ptr [[TMP6]], i32 0
153+ ; CHECK-NEXT: store <4 x i8> [[TMP4]], ptr [[TMP7]], align 8
154+ ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
155+ ; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i32 [[INDEX_NEXT]], 100
156+ ; CHECK-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
157+ ; CHECK: middle.block:
158+ ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 100, 100
159+ ; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
160+ ; CHECK: scalar.ph:
161+ ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i8 [ 100, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
162+ ; CHECK-NEXT: br label [[LOOP:%.*]]
163+ ; CHECK: loop:
164+ ; CHECK-NEXT: [[IV:%.*]] = phi i8 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
165+ ; CHECK-NEXT: [[L:%.*]] = ashr i32 [[F]], 18
166+ ; CHECK-NEXT: [[L_T:%.*]] = trunc i32 [[L]] to i8
167+ ; CHECK-NEXT: [[IV_EXT:%.*]] = zext i8 [[IV]] to i64
168+ ; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[IV_EXT]]
169+ ; CHECK-NEXT: store i8 [[L_T]], ptr [[GEP]], align 8
170+ ; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
171+ ; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[IV_NEXT]] to i32
172+ ; CHECK-NEXT: [[C:%.*]] = icmp ne i32 [[CONV]], 100
173+ ; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP7:![0-9]+]]
174+ ; CHECK: exit:
175+ ; CHECK-NEXT: ret void
176+ ;
177+ entry:
178+ br label %loop
179+
180+ loop:
181+ %iv = phi i8 [ 0 , %entry ], [ %iv.next , %loop ]
182+ %l = ashr i32 %f , 18
183+ %l.t = trunc i32 %l to i8
184+ %iv.ext = zext i8 %iv to i64
185+ %gep = getelementptr inbounds i8 , ptr %dst , i64 %iv.ext
186+ store i8 %l.t , ptr %gep , align 8
187+ %iv.next = add i8 %iv , 1
188+ %conv = zext i8 %iv.next to i32
189+ %c = icmp ne i32 %conv , 100
190+ br i1 %c , label %loop , label %exit
191+
192+ exit:
193+ ret void
194+ }
195+
70196define void @test_lshr_by_18 (ptr %A ) {
71197; CHECK-LABEL: define void @test_lshr_by_18
72198; CHECK-SAME: (ptr [[A:%.*]]) {
@@ -88,7 +214,7 @@ define void @test_lshr_by_18(ptr %A) {
88214; CHECK-NEXT: store <4 x i8> [[TMP6]], ptr [[TMP3]], align 8
89215; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
90216; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[INDEX_NEXT]], 100
91- ; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4 :![0-9]+]]
217+ ; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8 :![0-9]+]]
92218; CHECK: middle.block:
93219; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 100, 100
94220; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
@@ -107,7 +233,7 @@ define void @test_lshr_by_18(ptr %A) {
107233; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
108234; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[IV_NEXT]] to i32
109235; CHECK-NEXT: [[C:%.*]] = icmp ne i32 [[CONV]], 100
110- ; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP5 :![0-9]+]]
236+ ; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP9 :![0-9]+]]
111237; CHECK: exit:
112238; CHECK-NEXT: ret void
113239;
@@ -157,7 +283,7 @@ define void @test_lshr_by_4(ptr %A) {
157283; CHECK-NEXT: store <4 x i8> [[TMP10]], ptr [[TMP3]], align 8
158284; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
159285; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i32 [[INDEX_NEXT]], 100
160- ; CHECK-NEXT: br i1 [[TMP11]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6 :![0-9]+]]
286+ ; CHECK-NEXT: br i1 [[TMP11]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP10 :![0-9]+]]
161287; CHECK: middle.block:
162288; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 100, 100
163289; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
@@ -176,7 +302,7 @@ define void @test_lshr_by_4(ptr %A) {
176302; CHECK-NEXT: [[IV_NEXT]] = add i8 [[IV]], 1
177303; CHECK-NEXT: [[CONV:%.*]] = zext i8 [[IV_NEXT]] to i32
178304; CHECK-NEXT: [[C:%.*]] = icmp ne i32 [[CONV]], 100
179- ; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP7 :![0-9]+]]
305+ ; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP11 :![0-9]+]]
180306; CHECK: exit:
181307; CHECK-NEXT: ret void
182308;
@@ -209,4 +335,8 @@ exit:
209335; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}
210336; CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]}
211337; CHECK: [[LOOP7]] = distinct !{[[LOOP7]], [[META2]], [[META1]]}
338+ ; CHECK: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]}
339+ ; CHECK: [[LOOP9]] = distinct !{[[LOOP9]], [[META2]], [[META1]]}
340+ ; CHECK: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]], [[META2]]}
341+ ; CHECK: [[LOOP11]] = distinct !{[[LOOP11]], [[META2]], [[META1]]}
212342;.
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